The present subject matter generally relates to a capacitor assembly. More particularly, the present subject matter relates to a multilayer ceramic capacitor assembly for enhanced high frequency performance. Most particularly, the present subject matter relates to a multilayer ceramic capacitor assembly capable of exhibiting lower high-frequency inductance and a controlled equivalent series resistance (ESR).
The development of higher speed microprocessor chips and the miniaturization of both the power conversion circuitry used to power those chips and the circuitry they drive have led to an increase in the demand for small footprint, low inductance capacitors that have a useful ESR value while maintaining an effective capacitance. The need for such capacitors is due to the unintended generation of power supply noise (i.e., voltage fluctuations) across the power supply buses, a result of the simultaneous switching of logic gates during current flow. Such voltage fluctuations may have the undesirable result of causing unintended logic gate switching.
In order to manage this noise problem, decoupling capacitors acting as local energy sources for switching and refreshing logic gates within the circuitry are used. However, as the industry moves toward lower-voltage higher-frequency operating systems, the need exists for a controlled ESR low inductance capacitor that by design maintains its capacitance and minimizes its inductance while increasing its equivalent series resistance. Such a capacitor would have the capability to withstand the power spikes within any voltage fluctuations while serving as a source of energy for refreshing the logic gates connected thereto.
Previously, low inductance wound capacitors have been provided by flattening wound, extended foil sections and welding the extending foil sections to terminal pieces or even edge-welding the foils in spaced positions along the extended foil sections. Other wound capacitors have provided both low inductance and low ESR performance by deforming the extended foil edges, preferably by sawing, to generate metallurgical bonds. Tabs were attached near the foil ends thus providing a round, rolled capacitor without requiring the insertion of multiple tabs during the rolling process. Such a capacitor is disclosed in U.S. Pat. No. 4,509,100 (Puppolo), which is fully incorporated herein by reference.
Another capacitor, a multi-element capacitor, allowing for a lower impedance and lower ESR was provided through the use of a ceramic electrode/metallic electrode combination with a very specific dielectric material used for the ceramic capacitive elements. Such capacitor is disclosed in U.S. Pat. No. 5,973,907 (Reed), which is fully incorporated herein by reference.
While useful for their purpose, neither of the above approaches allows for an increase in the ESR of a capacitor while maintaining low inductance and the effective capacitance of the device. Still further, none of the previous approaches may function effectively during operation of the device at the higher frequencies required by today's electronics. Today's systems use many capacitors in parallel, therefore, combined resistance (impedance) in the circuits is extremely low, especially at the circuits resonant frequency. The circuit has a natural tendency to ring at such frequency and the harmonics of its resonant frequency. This phenomenon creates unwanted electrical noise in the circuit and can lead to an undesirably excessive emission of radio frequency (RF) signals. Small increases in ESR can suppress these undesired phenomena. Furthermore, a controlled circuit impedance typically allows better matching between adjacent functional stages of an electronic device as well as increased power transfer from a power supply to functioning integrated circuit (IC), application specific integrated circuit (ASIC), processor, or other component. Simultaneously, only by maintaining a low inductance and its effective capacitance will the device continue to serve its function in the circuit.
Other known capacitor embodiments claim to provide improved ESR properties. For example, U.S. Pat. No. 4,164,006 (Kolkowski) and U.S. Pat. No. 4,107,834 (Kolkowski) respectively disclose a capacitor with minimized ESR at standard frequencies of operation and a corresponding method for making the same. U.S. Pat. No. 4,499,524 (Shioleno) provides a multilayer ceramic (MLC) capacitor with improved ESR and impedance characteristics. A capacitor with low ESR and low rates of change in ESR is disclosed in U.S. Pat No. 5,006,964 (Ross et al.)
Still further known capacitor technologies are directed to improved inductance characteristics. U.S. Pat. No. 4,853,827 (Hernandez) concerns a multilayer capacitor with alternating conductive and dielectric layers that provides generally high capacitance and low inductance. U.S. Pat. No. 5,313,363 (Arbanas) is discloses a low impedance assembly for use in high frequency applications. A capacitor module designed to provide a minimal amount of stray inductance is the subject of U.S. Pat. No. 5,142,439 (Huggett et al.), and U.S. Pat. No. 4,916,576 (Herbert et al.) concerns a multipin matrix capacitor, aspects of which provide for reduced inductance qualities.
Still further known electronic devices are designed with other particular performance characteristics in mind. U.S. Pat. No. 5,486,277 (Barbee, Jr. et al.) and U.S. Pat. No. 5,414,588 (Barbee, Jr. et al.) disclose high performance capacitors with high energy density, high specific energy, and high voltage breakdown. U.S. Pat. No. 5,729,450 (Dimino et al.) concerns a capacitor that generally offers improved performance over a wider frequency range of operation.
Certain desirable capacitor configurations are achieved with aspects of peripheral terminations comprising a plurality of termination layers. U.S. Pat. No. 4,740,863 (Langlois) and U.S. Pat. No. 5,712,758 (Amano et al.) disclose MLC capacitors with multi-layered end terminations.
Additional background references that concern multi-layered electronic structures or materials for making such devices include U.S. Pat. No. 5,185,690 (Miller), U.S. Pat. No. 5,952,040 (Yadav et al.), U.S. Pat. No. 5,808,856 (Bischoff et al.), U.S. Pat. No. 5,680,685 (Bischoff), U.S. Pat. No. 5,603,147 (Bischoff et al.), U.S. Pat. No. 4,949,217 (Ngo), U.S. Pat. No. 4,704,657 (Yokoe et al.) and U.S. Pat. No. 5,132,613 (Papae et al.)
Based on the needs of present technology and the shortcomings of known capacitor configurations, it is desirable to provide a controlled ESR, low inductance capacitor capable of operating at the higher frequencies required by today's electronic systems. In particular, it is desirable to provide a controlled ESR, low inductance multilayer ceramic capacitor that can operate to filter voltage fluctuations while providing the energy required to refresh the logic gates within the circuitry to which it is attached.
While various aspects and alternative features are known in the field of multilayered capacitors and other specialized electronic devices, no one design has emerged that generally addresses all of the issues as discussed herein. The disclosures of all the foregoing United States patents are hereby fully incorporated into this application for all purposes by reference thereto.